Cache in ARM Cortex M7: Cache Handling – EmbeddedExpertIO In order to solve the coherency issue of the cache, we need to clean the data cache of ARM Cortex M7 before the data is read by the DMA and invalidate the cache after the DMA has written the data to the SRAM
Maintaining CPU data cache coherence for DMA buffers This topic is inspired by discussions in ST forum and ARM forum, where a proper cache maintenance was sorted out and an example of a real-life speculative read was detected
Managing Cache Coherency on Cortex-M7 Based MCUs Another way to avoid cache coherency is to use Tightly Coupled Memory (TCM) as the contents of TCM are not cached and can be accessed by both the CPU and the DMA
Arm Cortex-M7 Processor Technical Reference Manual r1p2 This section describes the behavior of the optional L1 caches in the Cortex-M7 processor memory system The memory system is configured during implementation and can include instruction and data caches of varying sizes
Data corruption issue with DMA operations on ARM Cortex-M7 (STM32F7 . . . There are three standard approaches that can be employed to solve this: Use a special instruction to clean the cache before initiating the DMA Tx transfer, forcing the MCU to write the cache contents to RAM (so that they can then be read by DMA)
[RFC] DMA and Data cache coherency on arm M7 devices On the ARM-M7 core-based stm32 MCU, when the L1-Cache memory is enabled, the system needs to "ensure data coherency between the core and the main memory when dealing with shared data", especially with DMA transfers
Dm00272913 Level 1 Cache On Stm32f7 Series and Stm32h7 Series . . . It provides insights on cache control, maintenance operations, and strategies to ensure data coherency between the CPU and DMA The document also includes best practices and common mistakes to avoid when working with cache in these devices